Abstract:
In this paper, with the help of simulations the concepts of source/drain (S/D) impurity profile engineering are proposed for reduction of the junction capacitance (Cj). It has been recently shown that it is possible to realize the benefits of PD- SOI technologies with the help of Source/Drain On Depletion Layer (SDODEL) MOSFETs, employing the bulk technologies. Here, for the first time, we investigated analog performance improvement with Single Halo SDODEL MOSFETs, as well as Double Halo SDODEL MOSFET and compared their performances with Double Halo MOSFETs (which will henceforth be referred as Control MOSFETs) with extensive process and device simulations. Our results show that, in Single Halo SDODEL MOSFET there is a significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/IDetc.) for sub 100nm technologies.
