8-bit 2-GS/s 20.5 mW Flash Assisted Time Interleaving SAR ADC for Direct Sampling RF Receivers

Abstract

This paper reports a flash-assisted time-interleaved sar (fati-sar) adc for digitizing the rf signal directly. The adc provides the highest conversion speed per channel. In the proposed architecture, the key idea is to use the merged capacitor switching (mcs) technique to make energy efficient sar adc. An extra clock cycle is used to provide increased resolution without using power-consuming calibration circuits. The adc is simulated in a 40nm standard digital cmos process. It achieves 7.16 bit enob, 44.86 db sinad, 60.91 dbc sfdr at 2 gs/s with a nyquist rate input signal. The power consumption is 20.5 mw from a 1.1 v supply, which corresponds to 71.67 fj/conversion-step fomw and 151.74 db foms. © 2021 ieee.