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Showing 10 out of a total of 14 results for community: IITB Publications. (0.012 seconds)

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Porphyrin Self-Assembled Monolayer as a Copper Diffusion Barrier for Advanced CMOS Technologies

KHADERBAD, MA; PANDHARIPANDE, R; SINGH, V; MADHU, S; RAVIKANTH, M; RAO, VR (IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2012)
OFET based explosive sensors using diketopyrrolopyrrole and metal organic framework composite active channel material

SURYA, SG; NAGARKAR, SS; GHOSH, SK; SONAR, P; RAO, VR (ELSEVIER SCIENCE SA, 2016)
A Vapor Phase Self-Assembly of Porphyrin Monolayer as a Copper Diffusion Barrier for Back-End-of-Line CMOS Technologies

NAIK, TR; SINGH, V; RAVIKANTH, M; RAO, VR (IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2016)
Effect of Metal Gate Granularity Induced Random Fluctuations on Si Gate-All-Around Nanowire MOSFET 6-T SRAM Cell Stability

BAJAJ, M; NAYAK, K; GUNDAPANENI, S; RAO, VR (IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2016)
Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits

NAYAK, K; BAJAJ, M; KONAR, A; OLDIGES, PJ; IWAI, H; MURALI, KVRM; RAO, VR (IOP PUBLISHING LTD, 2014)
Investigations of enhanced device characteristics in pentacene-based field effect transistors with sol-gel interfacial layer

CAHYADI, T; TEY, JN; MHAISALKAR, SG; BOEY, F; RAO, VR; LAL, R; HUANG, ZH; QI, GJ; CHEN, ZK; NG, CM (AMER INST PHYSICS, 2007)
Implications of fin width scaling on variability and reliability of high-k metal gate FinFETs

CHABUKSWAR, S; MAJI, D; MANOJ, CR; ANIL, KG; RAO, VR; CRUPI, F; MAGNONE, P; GIUSI, G; PACE, C; COLLAERT, N (ELSEVIER SCIENCE BV, 2010)
Fabrication and Analysis of a Si/Si0.55Ge0.45 Heterojunction Line Tunnel FET

WALKE, AM; VANDOOREN, A; ROOYACKERS, R; LEONELLI, D; HIKAVYY, A; LOO, R; VERHULST, AS; KAO, KH; HUYGHEBAERT, C; GROESENEKEN, G; RAO, VR; BHUWALKA, KK; HEYNS, MM; COLLAERT, N; THEAN, AVY (IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2014)
Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs

NAYAK, K; AGARWAL, S; BAJAJ, M; OLDIGES, PJ; MURALI, KVRM; RAO, VR (IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2014)
1/f Noise in Drain and Gate Current of MOSFETs With High-k Gate Stacks

MAGNONE, P; CRUPI, F; GIUSI, G; PACE, C; SIMOEN, E; CLAEYS, C; PANTISANO, L; MAJI, D; RAO, VR; SRINIVASAN, P (IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2009)

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