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dc.contributor.authorPAUL, Aen_US
dc.contributor.authorCHSRIDHARen_US
dc.contributor.authorGEDAM, Sen_US
dc.contributor.authorMAHAPATRA, Sen_US
dc.date.accessioned2009-01-05T13:00:47Zen_US
dc.date.accessioned2011-11-28T07:04:27Zen_US
dc.date.accessioned2011-12-15T09:56:42Z
dc.date.available2009-01-05T13:00:47Zen_US
dc.date.available2011-11-28T07:04:27Zen_US
dc.date.available2011-12-15T09:56:42Z
dc.date.issued2006en_US
dc.identifier.citationProceedings of the International Electron Devices Meeting, San Francisco, USA, 11-13 December 2006, 1-4en_US
dc.identifier.isbn1-4244-0439-8en_US
dc.identifier.uri10.1109/IEDM.2006.346793en_US
dc.identifier.urihttp://hdl.handle.net/10054/548en_US
dc.identifier.urihttp://dspace.library.iitb.ac.in/xmlui/handle/10054/548en_US
dc.description.abstractA simulator is developed for SONOS flash memories to predict program (P), erase (E) and retention (R) behavior under uniform ID operation. It provides insight on the impact of trap parameters on P, E and R and can be used to optimize memory stacks.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectFlash Memoriesen_US
dc.subjectLogic Simulationen_US
dc.subjectOptimisationen_US
dc.titleComprehensive simulation of program, erase and retention in charge tapping flash memoriesen_US
dc.typeArticleen_US
dc.description.copyright© IEEEen_US


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