Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectrics

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Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectrics

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dc.contributor.author MOHAPATRA, NR en_US
dc.contributor.author DUTTA, A en_US
dc.contributor.author DESAI, MP en_US
dc.contributor.author RAMGOPAL RAO, V en_US
dc.date.accessioned 2008-12-12T04:47:32Z en_US
dc.date.accessioned 2011-11-28T09:25:09Z en_US
dc.date.accessioned 2011-12-15T09:58:13Z
dc.date.available 2008-12-12T04:47:32Z en_US
dc.date.available 2011-11-28T09:25:09Z en_US
dc.date.available 2011-12-15T09:58:13Z
dc.date.issued 2001 en_US
dc.identifier.citation Proceedings of the Fourteenth International Conference on VLSI Design, Banglore, India, 3-7 January 2001, 479-482 en_US
dc.identifier.isbn 0-7695-0831-6 en_US
dc.identifier.uri 10.1109/ICVD.2001.902704 en_US
dc.identifier.uri http://hdl.handle.net/10054/309 en_US
dc.identifier.uri http://dspace.library.iitb.ac.in/xmlui/handle/10054/309 en_US
dc.description.abstract In this paper we look at the quantitative picture of fringing field effects by use of high-k dielectrics on the 70 nm node CMOS technologies. By using Monte-Carlo based techniques, we extract the degradation in gate-to-channel capacitance and the internal and external fringing capacitance components for varying values of K. The results clearly show the decrease in external fringing capacitance, increase in internal fringing capacitance and a slight decrease in overall capacitance, when the conventional SiO2 is replaced by high-K dielectric. From the circuit point of view the lower total capacitance will increase the speed of the device, while the internal fringing capacitance will degrade the short-channel performance contributing to higher DIBL and drain leakage. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject cmos integrated circuit en_US
dc.subject dielectric materials en_US
dc.subject monte carlo methods en_US
dc.subject leakage currents en_US
dc.title Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectrics en_US
dc.type Article en_US
dc.description.copyright © IEEE en_US


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