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dc.contributor.authorMAHAPATRA, Sen_US
dc.contributor.authorRAMGOPAL RAO, Ven_US
dc.contributor.authorVASI, Jen_US
dc.contributor.authorCHENG, Ben_US
dc.contributor.authorWOO, JCSen_US
dc.date.accessioned2008-12-08T08:41:15Zen_US
dc.date.accessioned2011-11-27T13:11:28Zen_US
dc.date.accessioned2011-12-15T09:56:38Z
dc.date.available2008-12-08T08:41:15Zen_US
dc.date.available2011-11-27T13:11:28Zen_US
dc.date.available2011-12-15T09:56:38Z
dc.date.issued2000en_US
dc.identifier.citationProceeding of the IEEE International Integrated Reliability Workshop Final Report, Lake Tahoe, USA, 23-26 October 2000, 29-31en_US
dc.identifier.isbn0-7803-6392-2en_US
dc.identifier.uri10.1109/IRWS.2000.911895en_US
dc.identifier.urihttp://hdl.handle.net/10054/228en_US
dc.identifier.urihttp://dspace.library.iitb.ac.in/xmlui/handle/10054/228en_US
dc.description.abstractSOI MNSFETs with channel lengths down to 100 nm and having a Jet Vapor Deposited (JVD) silicon nitride (Si3N4) gate dielectric are fabricated and characterized. The JVD MNSFETs show comparable performance in comparison to conventional SiO2 SOI-MOSFETs, in terms of low gate leakage, Si3N4/Si interface quality and Ion/I off ratio. In addition, the MNSFETs show better hot carrier reliability compared to conventional MOSFETs. Our results explore the worthiness of JVD Si3N4 as gate dielectric for future low power ULSI applications.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectMisfeten_US
dc.subjectHot Carriersen_US
dc.subjectLow-Power Electronicsen_US
dc.subjectSemiconductor Device Reliabilityen_US
dc.subjectSilicon-On-Insulatoren_US
dc.subjectVapour Deposited Coatingsen_US
dc.titleReliability studies on sub 100 nm SOI-MNSFETsen_US
dc.typeArticleen_US
dc.description.copyright© IEEEen_US


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