Reliability studies on sub 100 nm SOI-MNSFETs

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Reliability studies on sub 100 nm SOI-MNSFETs

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dc.contributor.author MAHAPATRA, S en_US
dc.contributor.author RAMGOPAL RAO, V en_US
dc.contributor.author VASI, J en_US
dc.contributor.author CHENG, B en_US
dc.contributor.author WOO, JCS en_US
dc.date.accessioned 2008-12-08T08:41:15Z en_US
dc.date.accessioned 2011-11-27T13:11:28Z en_US
dc.date.accessioned 2011-12-15T09:56:38Z
dc.date.available 2008-12-08T08:41:15Z en_US
dc.date.available 2011-11-27T13:11:28Z en_US
dc.date.available 2011-12-15T09:56:38Z
dc.date.issued 2000 en_US
dc.identifier.citation Proceeding of the IEEE International Integrated Reliability Workshop Final Report, Lake Tahoe, USA, 23-26 October 2000, 29-31 en_US
dc.identifier.isbn 0-7803-6392-2 en_US
dc.identifier.uri 10.1109/IRWS.2000.911895 en_US
dc.identifier.uri http://hdl.handle.net/10054/228 en_US
dc.identifier.uri http://dspace.library.iitb.ac.in/xmlui/handle/10054/228 en_US
dc.description.abstract SOI MNSFETs with channel lengths down to 100 nm and having a Jet Vapor Deposited (JVD) silicon nitride (Si3N4) gate dielectric are fabricated and characterized. The JVD MNSFETs show comparable performance in comparison to conventional SiO2 SOI-MOSFETs, in terms of low gate leakage, Si3N4/Si interface quality and Ion/I off ratio. In addition, the MNSFETs show better hot carrier reliability compared to conventional MOSFETs. Our results explore the worthiness of JVD Si3N4 as gate dielectric for future low power ULSI applications. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject misfet en_US
dc.subject hot carriers en_US
dc.subject low-power electronics en_US
dc.subject semiconductor device reliability en_US
dc.subject silicon-on-insulator en_US
dc.subject vapour deposited coatings en_US
dc.title Reliability studies on sub 100 nm SOI-MNSFETs en_US
dc.type Article en_US
dc.description.copyright © IEEE en_US


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