AHIR: a hardware intermediate representation for hardware generation from high-level programs

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AHIR: a hardware intermediate representation for hardware generation from high-level programs

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Title: AHIR: a hardware intermediate representation for hardware generation from high-level programs
Author: SAHASRABUDDHE, SAMEER D; RAJA, HAKIM; ARYA, KAVI; DESAI, MP
Abstract: We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to take advantage of optimisations available in the software compiler flow, and also to provide freedom to the low-level synthesiser, to explore options for application-specific implementations. Two operations become possible - reuse of computational resources across different modules in the design, and generation of an application-specific memory subsystem for faster data accesses. AHIR presents a decoupled view of the program, in terms of control flow, dataflow and memory accesses. Each module in AHIR is a triplet consisting of a control-path, datapath and a symbolic association between the two. Memory is represented only by load-store operators, while the memory subsystem is separately designed by the implementor. In the program-to-hardware flow, a module in AHIR corresponds to a function in C. A complete program is a call-graph of functions, which is translated to a set of modules. The call-graph is restricted to be a DAG; recursion is not allowed. The representation is generated by a back-end in the software compiler, which runs after all source-level optimisations have been performed by relevant passes.
URI: 10.1109/VLSID.2007.28
http://hdl.handle.net/10054/1647
http://dspace.library.iitb.ac.in/xmlui/handle/10054/1647
Date: 2007


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