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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/9072

Title: Design of a 0.1 mu m single halo (SH) thin film silicon-on-insulator (SOI) MOSFET for analogue applications
Authors: HAKIM, NUD
RAO, VR
VASI, J
Keywords: circuits
Issue Date: 2005
Publisher: IOP PUBLISHING LTD
Citation: SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 20(9), 895-902
Abstract: In this paper, we propose a design of a 0.1 mu m single halo (SH) thin film silicon-on-insulator (SOI) nMOSFET device for analogue and mixed signal applications. The single halo structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. The design methodology is based upon the improvement in the short-channel effects (SCE) and suppression of the kink. The device is optimized for various film thicknesses and different peak dopings. The position of the peak doping near the source is also an important parameter and hence, also needs to be optimized. The SH devices show better V-th-L roll-off, low drain induced barrier lowering, higher breakdown voltages and lower floating-body effects. The experimental results have shown the superior analogue performance of SH SOI MOSFETs. Also, the low drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance.
URI: http://dx.doi.org/10.1088/0268-1242/20/9/001
http://dspace.library.iitb.ac.in/xmlui/handle/10054/9072
http://hdl.handle.net/10054/9072
ISSN: 0268-1242
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