A reordering algorithm for data compression for FPGA configurations

Abstract

With the introduction of programmable logic devices with large capacities, the time taken to configure these devices has been of prime concern. One of the simplest solutions to reduce the configuration time is to compress the bit stream, as the compressed data would take lesser time to load on the device. Lossless compression can be achieved by using sophisticated algorithms but none of these algorithms have been able to achieve the theoretical limit to which the data can be compressed. This paper presents an algorithm for reordering the configuration bit stream prior to compression to improve upon the compression efficiency.