|
DSpace at IIT Bombay >
IITB Publications >
Article >
Please use this identifier to cite or link to this item:
http://dspace.library.iitb.ac.in/jspui/handle/10054/86
|
| Title: | Study of SILC and interface trap generation due to high field stressing and its operating temperature dependence in 2.2 nm gate dielectrics |
| Authors: | CHANDORKAR, AN
BORSE, DG
VAIDYA, SJ |
| Keywords: | mos capacitors
mos integrated circuits
vlsi
annealing
dielectric thin films
electron traps
integrated circuit measurement
integrated circuit reliability
leakage currents |
| Issue Date: | 2002 |
| Publisher: | IEEE |
| Citation: | IEEE Transactions on Electron Devices 49 (4), 699-701 |
| Abstract: | Reports study of metal-oxide-semiconductor (MOS) capacitors with 2.2 nm dry and N2O grown gate dielectrics. Interface trap generation during constant voltage stressing at different operating temperatures (from 22°C to 90°C) has been investigated. The effect of nitrogen annealing (20 min) at 400°C on high temperature stress-induced interface traps was also studied. |
| URI: | http://dx.doi.org/10.1109/16.992883
http://hdl.handle.net/10054/86
http://dspace.library.iitb.ac.in/xmlui/handle/10054/86 |
| ISSN: | 0018-9383 |
| Appears in Collections: | Article
|
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
|
