Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/xmlui/handle/10054/86
Title: Study of SILC and interface trap generation due to high field stressing and its operating temperature dependence in 2.2 nm gate dielectrics
Authors: CHANDORKAR, AN
BORSE, DG
VAIDYA, SJ
Keywords: Mos Capacitors
Mos Integrated Circuits
Vlsi
Annealing
Dielectric Thin Films
Electron Traps
Integrated Circuit Measurement
Integrated Circuit Reliability
Leakage Currents
Issue Date: 2002
Publisher: IEEE
Citation: IEEE Transactions on Electron Devices 49 (4), 699-701
Abstract: Reports study of metal-oxide-semiconductor (MOS) capacitors with 2.2 nm dry and N2O grown gate dielectrics. Interface trap generation during constant voltage stressing at different operating temperatures (from 22°C to 90°C) has been investigated. The effect of nitrogen annealing (20 min) at 400°C on high temperature stress-induced interface traps was also studied.
URI: http://dx.doi.org/10.1109/16.992883
http://hdl.handle.net/10054/86
http://dspace.library.iitb.ac.in/xmlui/handle/10054/86
ISSN: 0018-9383
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