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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/8532

Title: Parasitic effects in multi-gate MOSFETs
Authors: KOBAYASHI, Y
MANOJ, CR
TSUTSUI, K
HARIHARAN, V
KAKUSHIMA, K
RAO, VR
AHMET, P
IWAI, H
Keywords: finfet
Issue Date: 2007
Publisher: IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation: IEICE TRANSACTIONS ON ELECTRONICS, E90C(10), 2051-2056
Abstract: In this paper, we have systematically investigated parasitic effects due to the gate and source-drain engineering in multi-gate transistors. The potential impact of high-K dielectrics on multi-gate MOSFETs (MuGFETs), such as FinFET, is evaluated through 2D and 3D device simulations over a wide range of proposed dielectric values. It is observed that introduction of high-K dielectrics will significantly degrade the short channel effects (SCEs), however a combination of oxide and high-K stack can effectively control this degradation. The degradation is mainly due to the increase in the internal fringe capacitance coupled with the decrease in gate-channel capacitance. From the circuit perspective, an optimum K value has been identified through mixed mode simulations. Further, as a part of this work, the importance of optimization of the shape of the spacer region is highlighted through full 3D simulations.
URI: http://dx.doi.org/10.1093/ietele/e90-c.10.2051
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8532
http://hdl.handle.net/10054/8532
ISSN: 0916-8524
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