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|Title: ||Performance and Reliability Study of Single-Layer and Dual-Layer Platinum Nanocrystal Flash Memory Devices Under NAND Operation|
|Authors: ||SINGH, PK|
|Keywords: ||design optimization|
|Issue Date: ||2010|
|Publisher: ||IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC|
|Citation: ||IEEE TRANSACTIONS ON ELECTRON DEVICES, 57(8), 1829-1837|
|Abstract: ||Memory window (MW) and the retention of single-layer (SL) and dual-layer (DL) platinum (Pt) nanocrystal (NC) devices are extensively studied before and after program/erase (P/E) cycling. DL devices show better charge storage capability and reliability over the SL devices. Up to 50% improvement in the stored charge is estimated in the DL device over SL when P/E is performed at equal field. Excellent high temperature and postcycling retention capabilities of SL and DL devices are shown. The impact of the interlayer film (ILF) thickness on the retention of the DL structure is reported. While SL devices show poor P/E cycling endurance, DL cycling is shown to meet the minimum requirements of the multilevel cell (MLC) operation.|
|Appears in Collections:||Article|
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