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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/8436

Title: Part II: A Novel Scheme to Optimize the Mixed-Signal Performance and Hot-carrier Reliability of Drain-Extended MOS Devices
Authors: SHRIVASTAVA, M
BAGHINI, MS
GOSSNER, H
RAO, VR
Keywords: channel mosfets
n-channel
degradation
model
injection
generation
breakdown
Issue Date: 2010
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: IEEE TRANSACTIONS ON ELECTRON DEVICES, 57(2), 458-465
Abstract: The impact of scaling the depth of the shallow trench isolation (STI) region, underneath the gate-to-drain overlap, on the STI drain-extended metal-oxide-semiconductor (DeMOS) mixed-signal performance and hot-carrier behavior is systematically investigated in this work. For the first time, we discuss a dual-STI process for input/output applications. Furthermore, the differences in the hot-carrier behavior of various drain-extended devices are studied under the ON-and OFF-states. We found that the non-STI DeMOS devices are quite prone to failure when compared with the STI DeMOS devices in both the ON-and OFF-states. We introduced a more accurate way of predicting hot-carrier degradation in these types of devices in the ON-state. We show that scaling the depth of the STI underneath the gate is the key for improving both the mixed-signal and hot-carrier reliability performances of these devices.
URI: http://dx.doi.org/10.1109/TED.2009.2036799
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8436
http://hdl.handle.net/10054/8436
ISSN: 0018-9383
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