Please use this identifier to cite or link to this item:
Title: Silicon film thickness optimization for SOI-DTMOS from circuit performance considerations
Authors: DESAI, MP
Keywords: Mosfet
Delay Circuit
Semiconductor Device Models
Thick Films
Issue Date: 2004
Publisher: IEEE
Citation: IEEE Electron Device Letters 25 (6), 436-38
Abstract: The performance of partially depleted silicon-on-insulator (PDSOI) dynamic threshold MOSFET (DTMOS) devices is degraded by the body capacitance and body resistance, which depend strongly on the silicon film thickness. We show that the body RC time constant reduces up to a certain value of silicon film thickness, and then saturates. However, delay of a DTMOS circuit is affected not only by the RC delay of the body but also by the additional load capacitance, which appears due to the gate to body contact. In this paper, we propose a model for PDSOI-DTMOS circuit delay, taking the effect of body parasitics into account, and use it to study the circuit delay as a function of silicon film thickness. Using this model, we show that the optimum value of silicon film thickness is approximately equal to the depletion width in the silicon film in a typical sub-100-nm PDSOI-DTMOS technology.
ISSN: 0741-3106
Appears in Collections:Article

Files in This Item:
File Description SizeFormat 
1302251.pdf199.1 kBAdobe PDFThumbnail

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.