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|Title: ||Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors|
|Authors: ||MOHAPATRA, NR|
|Keywords: ||gate dielectrics|
|Issue Date: ||2003|
|Publisher: ||IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC|
|Citation: ||IEEE TRANSACTIONS ON ELECTRON DEVICES, 50(4), 959-966|
|Abstract: ||In deep submicrometer MOSFETs the device performances is limited by the parasitic capacitance. and resistance. Hence a circuit, model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thicknes, gate dielectric constant, and spacer width.|
|Appears in Collections:||Article|
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