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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/8348

Title: Impact of high-k gate dielectrics on the device and circuit performance of nanoscale FinFETs
Authors: MANOJ, CR
RAO, VR
Keywords: mosfets
nm
Issue Date: 2007
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: IEEE ELECTRON DEVICE LETTERS, 28(4), 295-297
Abstract: The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C-of in addition to an increase in the internal fringe capacitance C-if with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering.
URI: http://dx.doi.org/10.1109/LED.2007.892365
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8348
http://hdl.handle.net/10054/8348
ISSN: 0741-3106
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