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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/8346

Title: Impact of Fringe Capacitance on the Performance of Nanoscale FinFETs
Authors: MANOJ, CR
SACHID, AB
YUAN, F
CHANG, CY
RAO, VR
Keywords: double-gate
device
design
nm
Issue Date: 2010
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: IEEE ELECTRON DEVICE LETTERS, 31(1), 83-85
Abstract: In this letter, we report the enhanced fringe capacitance in FinFETs when compared to the equivalent planar MOSFETs at the 22-nm node. We show that this increase is due to the 3-D nature of the device and also due to the close proximity of the source/drain (S/D) epitaxial (epi) region to the metal gate. Using well-calibrated 3-D mixed-mode simulations, we show that this will cause the performance of FinFETs to be significantly degraded, unless proper device optimizations are carried out. Our results also indicate that the selective epi growth of S/D may adversely affect the overall performance of FinFETs, although it is effective in reducing series resistance. The increased parasitic components in FinFETs can be a serious issue for FinFET circuits with a large fan-out, and the solution lies in the aggressive fin pitch reduction, as shown in this letter.
URI: http://dx.doi.org/10.1109/LED.2009.2035934
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8346
http://hdl.handle.net/10054/8346
ISSN: 0741-3106
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