DSpace
 

DSpace at IIT Bombay >
IITB Publications >
Article >

Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/8332

Title: Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization
Authors: SACHID, AB
MANOJ, CR
SHARMA, DK
RAO, VR
Keywords: circuit performance
nanoscale finfets
dielectrics
mosfets
fibl
device
Issue Date: 2008
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: IEEE ELECTRON DEVICE LETTERS, 29(1), 128-130
Abstract: The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap regions as the technology scales down. We present a phenomenon called the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions. In these FinFETs, we show that the GFIBL can be effectively used to improve I-on. We propose the use of high-kappa spacers in such FinFETs to enhance the effect of GFIBL and thereby achieve better device and circuit performance. When compared with the underlap FinFETs with Si3N4 spacers, with kappa = 20 spacers, we show that it is possible to achieve an 80% increase in I-on at iso-I-off conditions and a 15% decrease in the inverter delay for a fan-out of four.
URI: http://dx.doi.org/10.1109/LED.2007.911974
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8332
http://hdl.handle.net/10054/8332
ISSN: 0741-3106
Appears in Collections:Article

Files in This Item:

File SizeFormat
Gate fringe-induced barrier lowering .pdf210.87 kBAdobe PDFView/Open
View Statistics

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

 

Valid XHTML 1.0! DSpace Software Copyright © 2002-2010  Duraspace - Feedback