DSpace at IIT Bombay >
IITB Publications >
Please use this identifier to cite or link to this item:
|Title: ||Extraction of the top and sidewall mobility in FinFETs and the impact of fin-patterning processes and gate dielectrics on-mobility|
|Authors: ||IYENGAR, VV|
DE MEYER, K
|Issue Date: ||2007|
|Publisher: ||IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC|
|Citation: ||IEEE TRANSACTIONS ON ELECTRON DEVICES, 54(5), 1177-1184|
|Abstract: ||In this paper, we propose a simple methodology for the extraction of the top and sidewall mobility in FinFET like triple-gate device architectures. The underlying assumptions are outlined and verified by simulations and experiments. Using this model, the top and sidewall mobility on both n- and p-channel FinFETs, fabricated with various fin-patterning processes and gate dielectrics, was extracted. It is shown that the choice of the hard mask and corner-rounding processes and the gate dielectric impacts the top and sidewall mobility differently. The proposed methodology provides a powerful tool for technologists to optimize the gate stack and fin-patterning processes. It also provides a simple model to capture the anisotropy of mobility in device and circuit simulators.|
|Appears in Collections:||Article|
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.