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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/8325

Title: Extraction of the top and sidewall mobility in FinFETs and the impact of fin-patterning processes and gate dielectrics on-mobility
Authors: IYENGAR, VV
KOTTANTHARAYI, A
TRANJAN, FM
JURCZAK, M
DE MEYER, K
Keywords: cmos
Issue Date: 2007
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: IEEE TRANSACTIONS ON ELECTRON DEVICES, 54(5), 1177-1184
Abstract: In this paper, we propose a simple methodology for the extraction of the top and sidewall mobility in FinFET like triple-gate device architectures. The underlying assumptions are outlined and verified by simulations and experiments. Using this model, the top and sidewall mobility on both n- and p-channel FinFETs, fabricated with various fin-patterning processes and gate dielectrics, was extracted. It is shown that the choice of the hard mask and corner-rounding processes and the gate dielectric impacts the top and sidewall mobility differently. The proposed methodology provides a powerful tool for technologists to optimize the gate stack and fin-patterning processes. It also provides a simple model to capture the anisotropy of mobility in device and circuit simulators.
URI: http://dx.doi.org/10.1109/TED.2007.894937
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8325
http://hdl.handle.net/10054/8325
ISSN: 0018-9383
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