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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/8323

Title: Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation
Authors: NAIR, DR
MAHAPATRA, S
SHUKURI, S
BUDE, JD
Keywords: enhanced gate current
technological parameters
vlsi mosfets
part ii
cells
memory
Issue Date: 2005
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: IEEE TRANSACTIONS ON ELECTRON DEVICES, 52(4), 534-540
Abstract: The impact of program/erase (P/E) cycling on drain disturb in NOR Flash EEPROM cells under channel hot electron (CHE) and channel-initiated secondary electron (CHISEL) programming operation is studied. Charge gain disturb increases and charge loss disturb decreases after cycling under CHE and CHISEL operation. Carefully designed experiments and fullband Monte Carlo simulations were used to explain this behavior. P/E cycling induced degradation in gate coupling coefficient and the resulting increase in. source/drain leakage, reduction in hand-to-hand tunneling and change in carrier injection area seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.
URI: http://dx.doi.org/10.1109/TED.2005.844741
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8323
http://hdl.handle.net/10054/8323
ISSN: 0018-9383
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