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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/8291

Title: Device design and optimization considerations for bulk FinFETs
Authors: MANOJ, CR
NAGPAL, M
VARGHESE, D
RAO, VR
Keywords: double-gate
mosfets
simulation
nm
Issue Date: 2008
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: IEEE TRANSACTIONS ON ELECTRON DEVICES, 55(2), 609-615
Abstract: Fabrication of FinFETs using bulk CMOS instead of silicon on insulator (SOI) technology is of utmost interest as it reduces the process costs. Using well-calibrated device models and 3-D mixed mode simulations, we show that bulk FinFETs can be optimized with identical performances as that of SOI FinFETs. Optimized bulk FinFETs are compared with the corresponding SOI FinFETs for a range of technology nodes using an extensive simulation and design methodology. Further, we extend the concept of body doping in bulk FinFETs to the case of lightly doped fins unlike the heavily doped fin cases reported earlier. The optimum body doping required for bulk FinFETs, and its multiple advantages are also systematically evaluated. We also show that device parasitics play a crucial role in the optimization of nanoscale bulk FinFETs.
URI: http://dx.doi.org/10.1109/TED.2007.912996
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8291
http://hdl.handle.net/10054/8291
ISSN: 0018-9383
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