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|Title:||CHISEL flash EEPROM - Part II: Reliability|
|Keywords:||Enhanced Gate Current|
|Publisher:||IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC|
|Citation:||IEEE TRANSACTIONS ON ELECTRON DEVICES, 49(7), 1302-1307|
|Abstract:||In this work, we demonstrate the feasibility of using channel initiated secondary electron (CHISEL) programming in high density flash memories containing fully scaled memory cells. In Part I of this work, we discussed programming performance of scaled cells and cell channel length scaling issues. In Part 11, we discuss endurance and reliability of single cells and large arrays. We demonstrate from single cell measurements that after program/erase cycling, CHISEL operation shows lower threshold voltage window closure, lower program time degradation, reduced hole trapping, and device degradation, with a marginal increase in erase time compared to conventional channel hot electron (CHE) operation. The reasons for improved reliability of CHISEL operation are explained using device simulation. CHISEL programming also shows reduced charge gain drain disturb with only slightly higher charge loss drain disturb compared to CHE operation. Measurements on large 32-Mb array under CHISEL operation show tight threshold voltage distribution and more than ten years of data retention even after 100-k cycling. Results are presented showing excellent reliability of CHISEL programming operation for deeply scaled high density flash EEPROMs.|
|Appears in Collections:||Article|
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