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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/8252

Title: CHISEL flash EEPROM - Part I: Performance and scaling
Authors: MAHAPATRA, S
SHUKURI, S
BUDE, J
Keywords: enhanced gate current
vlsi mosfets
memory
cells
degradation
model
Issue Date: 2002
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: IEEE TRANSACTIONS ON ELECTRON DEVICES, 49(7), 1296-1301
Abstract: In this work, we demonstrate the feasibility of using channel initiated secondary electron (CHISEL) programming in high-density flash memories containing fully scaled memory cells. We discuss programming performance, cell channel length scaling, endurance, and reliability of single cells and large arrays. In Part I of this work, we show successful CHISEL programming operation in fully scaled flash cells having channel lengths down to 0.22 mum. Compared to conventional channel hot electron (CHE) programming, CHISEL operation shows faster programming for identical drain bias, and lower power consumption for similar programming speed. The effect of channel length scaling on CHISEL operation and related device optimization is discussed using measurements and device simulation. Measurement on optimized floating gate contacted devices having channel length down to 0.14 mum show good programming efficiency under CHISEL operation. The reliability and endurance of CHISEL operation in single cells and large arrays are discussed in Part 11 of this work.
URI: http://dx.doi.org/10.1109/TED.2002.1013289
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8252
http://hdl.handle.net/10054/8252
ISSN: 0018-9383
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