Assessment of SET logic robustness through noise margin modeling

Abstract

A compact model for noise margin (NM) of single-electron transistor (SET) logic is developed, which is a function of device capacitances and background charge (zeta). Noise margin is, then, used as a metric to evaluate the robustness of SET logic against background charge, temperature, and variation of SET gate and tunnel junction capacitances (C-G and C-T) It is shown that choosing alpha = C-T/C-G = 1/3 maximizes the NM. An estimate of the maximum tolerable zeta is shown to be equal to +/- 0.03e. Finally, the effect of mismatch in device parameters on the NM is studied through exhaustive simulations, which indicates that alpha is an element of [0.3, 0.4] provides maximum robustness. It is also observed that mismatch can have a significant impact on static power dissipation.