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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/8242

Title: Assessment of SET logic robustness through noise margin modeling
Authors: SATHE, C
DAN, SS
MAHAPATRA, S
Keywords: single-electron transistor
circuits
devices
simulator
design
Issue Date: 2008
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: IEEE TRANSACTIONS ON ELECTRON DEVICES, 55(3), 909-915
Abstract: A compact model for noise margin (NM) of single-electron transistor (SET) logic is developed, which is a function of device capacitances and background charge (zeta). Noise margin is, then, used as a metric to evaluate the robustness of SET logic against background charge, temperature, and variation of SET gate and tunnel junction capacitances (C-G and C-T) It is shown that choosing alpha = C-T/C-G = 1/3 maximizes the NM. An estimate of the maximum tolerable zeta is shown to be equal to +/- 0.03e. Finally, the effect of mismatch in device parameters on the NM is studied through exhaustive simulations, which indicates that alpha is an element of [0.3, 0.4] provides maximum robustness. It is also observed that mismatch can have a significant impact on static power dissipation.
URI: http://dx.doi.org/10.1109/TED.2007.915086
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8242
http://hdl.handle.net/10054/8242
ISSN: 0018-9383
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