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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/8198

Title: A Novel Table-Based Approach for Design of FinFET Circuits
Authors: THAKKER, RA
SATHE, C
SACHID, AB
BAGHINI, MS
RAO, VR
PATIL, MB
Keywords: particle swarm optimization
mosfet model
simulation
device
performance
transistor
splines
impact
gate
Issue Date: 2009
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 28(7), 1061-1070
Abstract: A new lookup-table (LUT) approach, based on normalization of the drain current with an I(D)-V(G) template, is proposed for simulation of MOS transistor circuits. The LUT approach is validated by considering two examples and by comparing the LUT results with mixed-mode (device-circuit) simulation results. This approach is implemented in a circuit simulator and integrated, for the first time, with an optimizer to enable efficient design of circuits, particularly those involving novel technologies for which compact models are not fully developed. Three FinFET-based circuits are designed to demonstrate the effectiveness of the proposed environment. Furthermore, it is shown that the table-based platform can take into account variations in process, supply voltage, and temperature during the design.
URI: http://dx.doi.org/10.1109/TCAD.2009.2017431
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8198
http://hdl.handle.net/10054/8198
ISSN: 0278-0070
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