A Novel Gate-Assisted Reverse-Read Scheme to Control Bit Coupling and Read Disturb for Multibit/Cell Operation in Deeply Scaled Split-Gate SONOS Flash EEPROM Cells

Abstract

A dual-node split-gate silicon-oxide-nitride-oxide silicon cell with a novel read scheme is proposed for 2-bit/cell operation. Using suitable gate screening bias in reverse read, bit coupling can be reduced, even when low read V(D) is used to keep read disturb under control. The proposed read scheme maintains the memory window for dual-bit/cell operation for deeply scaled cells. Two-dimensional process, device, and Monte Carlo simulations are extensively used to design and understand cell operation.