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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/8193

Title: A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance
Authors: SHRIVASTAVA, M
BAGHINI, MS
SHARMA, DK
RAO, VR
Keywords: bulk finfets
gate
design
Issue Date: 2010
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: IEEE TRANSACTIONS ON ELECTRON DEVICES, 57(6), 1287-1294
Abstract: For the first time, we propose a novel bottom spacer fin-shaped field-effect-transistor (FinFET) structure for logic applications suitable for system-on-chip (SoC) requirements. The proposed device achieved improved short-channel, power-delay, and self-heating performance compared with standard silicon-on-insulator FinFETs. Process aspects of the proposed device are also discussed in this paper. Physical insight into the improvement toward the short-channel performance and power dissipation is given through a detailed 3-D device/mixed-mode simulation. The self-heating behavior of the proposed device is compared with standard FinFETs by using detailed electro-thermal simulations. The proposed device requires an extra process step but enables smaller electrical width for self-loaded circuits and is an excellent option for SoC applications.
URI: http://dx.doi.org/10.1109/TED.2010.2045686
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8193
http://hdl.handle.net/10054/8193
ISSN: 0018-9383
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