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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/8110

Title: Tabled logic programming based IP matching tool using forced simulation
Authors: ROOP, PS
SOWMYA, A
RAMESH, S
GUO, HF
Keywords: reuse
Issue Date: 2004
Publisher: IEE-INST ELEC ENG
Citation: IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 151(3), 199-208
Abstract: Automatic IP (intellectual property) matching is a key to the reuse of IP cores. A new tabled logic programming-based IP matching algorithm is given that can check whether a given programmable IP can be adapted to match a given specification. When such adaptation is possible, the algorithm also generates a device driver (an interface) to adapt the IP. Though simulation, refinement and bisimulation algorithms exist, they cannot be used to check the adaptability of an IP, which is the essence of reuse. The IP matching algorithm is based on a formal verification technique called forced simulation. A forced simulation matching algorithm is implemented using a tabled logic programming environment, which provides distinct advantages for encoding such an algorithm. The tool has been used to match several specifications to programmable IN, achieving on an average 12 times speedup and 64% reduction in code size in comparison with previously published algorithms.
URI: http://dx.doi.org/10.1049/ip-cdt:20040502
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8110
http://hdl.handle.net/10054/8110
ISSN: 1350-2387
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