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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/80

Title: The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance
Authors: DESAI, MP
MOHAPATRA, NR
NARENDRA, SG
RAMGOPAL RAO, V
Keywords: computer simulation
electric insulators
monte carlo methods
capacitance
Issue Date: 2002
Publisher: IEEE
Citation: IEEE Transactions on Electron Devices 49 (5), 826-31
Abstract: The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (Kgate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum Kgate for different target subthreshold leakage currents has been identified.
URI: http://dx.doi.org/10.1109/16.998591
http://hdl.handle.net/10054/80
http://dspace.library.iitb.ac.in/xmlui/handle/10054/80
ISSN: 0018-9383
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