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Title: Estimation of process variation impact on DG-FinFET device performance using Plackett-Burman design of experiment method
Keywords: Design Of Experiments
Field Effect Transistors
Gates (Transistor)
Integrated Circuits
Issue Date: 2008
Publisher: IEEE
Citation: Proceedings of the 9th International Conference on Solid-State and Integrated-Circuit Technology, Beijing, China, 20-23 Octomber 2008, 215-218
Abstract: This paper studies various Double-Gate (DG) FinFET structures optimized for better “off state” and “on state” performance. In this work, we study the impact of process variation on the performance of DG-FinFET device with 20nm gate length. This was achieved through calibrated TCAD simulations. We show that the spacer thickness variation has the highest impact on Ion of the DG-FinFETs. In this work, we also have demonstrated the suitability of method of Plackett-Burman Design of Experiments (PB-DOE), for accurate estimation of the impact of the large number of process parameter-variations on DG-FinFET device’s electrical performance.
URI: 10.1109/ICSICT.2008.4734510
ISBN: 978-1-4244-2185-5
Appears in Collections:Proceedings papers

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