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Title: A novel dynamic threshold operation using electrically induced junction MOSFET in the deep sub-micrometer CMOS regime
Keywords: Cmos Integrated Circuit
Leakage Currents
Low-Power Electronics
Transient Analysis
Issue Date: 2003
Publisher: IEEE
Citation: Proceedings of the 16th International Conference on VLSI Design, New Delhi, India, 4-8 January 2003, 499-503
Abstract: The desired low power and high speed operation of CMOS integrated circuits is driving force for CMOS scaling into the sub-100 nm regime. In addition to the supply voltage, the threshold voltage needs to be scaled proportionately for low power operation. The idea of a Dynamic Threshold MOSFET (DTMOS), without the associated substrate loading effects, is a key to the problems involved in Sub-100 nm device scaling for low power CMOS. This work focuses on the device optimisation for such low power ULSI circuits using a novel implementation of Electrically Induced Junction (EJ)-MOSFET as a DTMOS. Such an implementation can be used without the additional substrate loading effects and the supply voltage limitations, commonly associated with conventional DTMOS operation. Our detailed DC as well as transient simulation results bring out the advantages of this novel structure.
URI: 10.1109/ICVD.2003.1183183
ISBN: 0-7695-1868-0
Appears in Collections:Proceedings papers

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