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|Title:||Channel engineering for high speed sub-1.0 V power supply deep sub-micron CMOS|
RAMGOPAL RAO, V
Electric Power Systems
|Citation:||Proceedings of the Symposium on VLSI Technology Digest of Technical Papers, Kyoto, Japan, 14-16 June 1999, 69-70|
|Abstract:||The effects of channel engineering on device performance have been extensively investigated. The lateral asymmetric channel (LAC) MOSFETs show significantly higher Idsat and gmsat, lower I off, and superior short-channel performance compared with double-halo (DH) and conventional MOSFETs by effectively utilizing the velocity overshoot effects. It is demonstrated that the device switching speed of the LAC device at VDD=0.6 V is equivalent to that of a conventional device operated at VDD=1.5 V|
|Appears in Collections:||Proceedings papers|
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