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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/548

Title: Comprehensive simulation of program, erase and retention in charge tapping flash memories
Authors: PAUL, A
CHSRIDHAR
GEDAM, S
MAHAPATRA, S
Keywords: flash memories
logic simulation
optimisation
Issue Date: 2006
Publisher: IEEE
Citation: Proceedings of the International Electron Devices Meeting, San Francisco, USA, 11-13 December 2006, 1-4
Abstract: A simulator is developed for SONOS flash memories to predict program (P), erase (E) and retention (R) behavior under uniform ID operation. It provides insight on the impact of trap parameters on P, E and R and can be used to optimize memory stacks.
URI: 10.1109/IEDM.2006.346793
http://hdl.handle.net/10054/548
http://dspace.library.iitb.ac.in/xmlui/handle/10054/548
ISBN: 1-4244-0439-8
Appears in Collections:Proceedings papers

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