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|Title:||Impact of substrate bias on p-MOSFET negative bias temperature instability|
|Authors:||BHARATH KUMAR, P|
Semiconductor Device Reliability
|Citation:||Proceedings of the 43rd Annual Reliability Physics Symposium, San Jose, USA, 17-21 April 2005, 700-701|
|Abstract:||Negative Bias Temperature Instability(NBTI)of p-MOSFET is an important reliability issues for digital as well as analog  CMOS circuits.Till date,characterization[3-9] and modelling [10-12] efforts to analyze NBTI machanism involve devices stressed eith zero substrate bias (VB).However,many circuits utilize nonzero VB to vary the device threshold voltage (VT),(e.g.for dual VT CMOS, standby leakage reduction,etc)[13-16].This paper aims to systematically study NBTI for VB>OV stress, which to the best of our knowledge has not been done so far.It is shown that NBTI increase for VB>OV stress.This is attributed to enhanced interface (NT)and bulk (NOT) trap generation due to impact ionization and hot-hole(HH)generation.The role of gate bias(VG),VB,temperature (T)and oxide thickness(TPHY) IS studied.This work would help all efforts in determining(i) reliability budget for any operating VB,(ii)proper choice of stress VB during accelerated aging tests,and (iii)suitable TCAD and SPICE models.|
|Appears in Collections:||Proceedings papers|
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