The study of damage generation in n-channel MOS transistors operating in the substrate enhanced gate current regime

Abstract

This paper analyzes in detail the damage generation in n-channel MOS transistors operating in the substrate enhanced gate current (SEGC) regime. The results are also compared with the damage generated during conventional hot carrier stress experiments. Stressing and charge pumping experiments are carried out to study the degradation with different substrate bias. Our results clearly show that the application of a substrate bias enhances degradation, which is strongly dependent on the transverse electric field and spread of the interface trap profile. The possible mechanisms responsible for such trends are discussed.