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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/526

Title: Cycling endurance of NOR flash EEPROM cells under CHISEL programming operation - impact of technological parameters and scaling
Authors: NAIR, DR
SHUKURI, S
MAHAPATRA, S
Keywords: nor circuits
flash memories
hot carriers
integrated circuit design
integrated circuit reliability
integrated circuit testing
logic design
Issue Date: 2004
Publisher: IEEE
Citation: IEEE Transactions on Electron Devices 51(10), 1672-1678
Abstract: The impact of technological parameter (channel doping, source/drain junction depth) variation and channel length scaling on the reliability of NOR flash EEPROM cells under channel initiated secondary electron (CHISEL) programming is studied. The best technology for CHISEL operation has been identified by using a number of performance metrics (cycling endurance of program/erase time, program/disturb margin) and scaling studies were done on this technology. It is explicitly shown that from a reliability perspective, bitcell optimization for CHISEL operation is quite different from that for channel hot electron (CHE) operation. Properly optimized bitcells show reliable CHISEL programming for floating gate length down to 0.2 μm.
URI: http://dx.doi.org/10.1109/TED.2004.835996
http://hdl.handle.net/10054/526
http://dspace.library.iitb.ac.in/xmlui/handle/10054/526
ISSN: 0018-9383
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