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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/476

Title: Built-in self-test technique for selective detection of neighbourhood pattern sensitive faults in memories
Authors: SABLE, RS
SARAF, RP
PAREKHJI, RA
CHANDORKAR, AN
Keywords: automatic test pattern generation
built-in self test
random-access storage
fault diagnosis
Issue Date: 2004
Publisher: IEEE
Citation: Proceedings of the 17th International Conference on VLSI Design, Mumbai, India, 5-9 January 2004, 753-756
Abstract: Traditional tests for memories are based on conventional fault models, involving the address decoder, individual memory cells and a limited coupling between them. The algorithms used in these tests have been successively augmented to consider stronger coupling conditions. Built-in self-test (BIST) solutions for testing memories today incorporate hardware for test pattern generation and application for a variety of these algorithms. This paper presents a BIST implementation for detection of neighbourhood pattern sensitive faults (NPSFs) in random access memories (RAMs). These faults are of different classes and types. More specifically, active, passive and static faults for distance 1 and 2 neighbourhoods, of types 1 and 2, are considered. It is shown how the proposed address generation and test pattern generation schemes can be made scaleable for the given fault type under consideration.
URI: 10.1109/ICVD.2004.1261019
http://hdl.handle.net/10054/476
http://dspace.library.iitb.ac.in/xmlui/handle/10054/476
ISBN: 0-7695-2072-3
Appears in Collections:Proceedings papers

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