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|Title:||Impact of technology scaling on metastability performance of CMOS synchronizing latches|
|Keywords:||Cmos Logic Circuit|
Integrated Circuit Design
|Citation:||Proceedings of the 7th Asia and South Pacific Design Automation Conference 15th International Conference on VLSI Design, Bangalore, India, 7-11 January 2002, 317-322|
|Abstract:||In this paper, we use circuit simulations to characterize the effects of technology scaling on the metastability parameters of CMOS latches used as synchronizers. We perform this characterization by obtaining a synchronization error probability curve from a histogram of the latch delay. The main metastability parameters of CMOS latches are τm and Tw. τm is the exponential time constant of the rate of decay of metastability and T w is effective metastability window size at a normal propagation delay. Both parameters can be extracted from a histogram of the latch delay. This paper also explains a way to calibrate the simulator for accuracy. The simulations indicate that τm scales better than the technology scale factor. Tw also scales down but its factor cannot be estimated as well as that of τ m. This is because Tw is a complex function of signal and clock edge rate and logic threshold level.|
|Appears in Collections:||Proceedings papers|
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