DSpace
 

DSpace at IIT Bombay >
IITB Publications >
Proceedings papers >

Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/413

Title: Fast DC analysis and its application to combinatorial optimization problems
Authors: TRIVEDI, GAURAV
DESAI, MP
NARAYANAN, H
Keywords: spice
circuit simulation
combinatorial mathematics
optimisation
Issue Date: 2006
Publisher: IEEE
Citation: Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems and Design, Hyderabad, India, 3-7 January 2006, 1-6
Abstract: Many combinatorial optimization problems such as the min cost flow problem are equivalent to the solution of appropriate DC circuits made up of positive resistors, voltage sources, current sources and ideal diodes. Simulating the DC circuit is an alternative approach to the approximate solution of such problems. However, conventional simulators such as SPICE are too slow for this purpose. This paper describes the structure and performance of a fast DC analyzer built at EE department, IIT Bombay specifically for solving large circuits consisting of positive resistors, voltage sources, current sources and diodes. Using the simulator, we have analyzed circuits composed of diodes, positive resistors, current and voltage sources of size up to 700,000 nodes and 1.2 million edges on a 3.0 GHz, 1GB RAM, PIV processor in at most 1.2 hrs. We also report a comparative study of the performance of our DC analyzer with that of fastest commercial simulator.
URI: 10.1109/VLSID.2006.89
http://hdl.handle.net/10054/413
http://dspace.library.iitb.ac.in/xmlui/handle/10054/413
ISBN: 0-7695-2502-4
Appears in Collections:Proceedings papers

Files in This Item:

File Description SizeFormat
1581537.pdf155.21 kBAdobe PDFView/Open
View Statistics

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

 

Valid XHTML 1.0! DSpace Software Copyright © 2002-2010  Duraspace - Feedback