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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/405

Title: A novel technique towards eliminating the global clock in VLSI circuits
Authors: HAZARI, G
DESAI, MP
GUPTA, A
CHAKRABORTY, SUPRATIK
Keywords: vlsi
control system synthesis
controllers
distributed control
Issue Date: 2004
Publisher: IEEE
Citation: Proceedings of the 17th International Conference on VLSI Design, Mumbai, India, 5-9 January 2004, 565-570
Abstract: As the feature size offered by VLSI technology shrinks, circuit performance as well as circuit complexity increases. This puts considerable pressure on the synchronous design methodology, mainly due to the difficulty of routing a low skew high frequency clock signal across a large die. On the other hand, the synchronous design methodology offers the benefits of a mature design flow and a comprehensive set of design tools. In this paper, we present an approach towards the elimination of the global clock signal in a synchronous design. We present a novel partitioning strategy and the design of a distributed asynchronous controller for this purpose. The transformed circuit can have performance comparable or possibly superior to the original synchronous circuit (provided clock could be distributed in the first place). The technique is demonstrated by a pilot design in a .18 micron TSMC process, and is a good candidate for a clock-less design methodology built around the principle of desynchronization.
URI: 10.1109/ICVD.2004.1260979
http://hdl.handle.net/10054/405
http://dspace.library.iitb.ac.in/xmlui/handle/10054/405
ISBN: 0-7695-2072-3
Appears in Collections:Proceedings papers

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