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Title: Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics
Keywords: Mosfet
Dielectric Thin Films
Semiconductor Device Models
Issue Date: 2003
Publisher: IEEE
Citation: Proceedings of the 16th International Conference on VLSI Design, New Delhi, India, 4-8 January 2003, 99-104
Abstract: This paper analyzes in detail the fringing induced barrier lowering (FIBL) in MOS transistors with high-k gate dielectrics using 2D device simulations. We found that the device short channel performance is degraded with increase in gate dielectric permittivity (K/sub gate/) due to an increase in the dielectric physical thickness to channel length ratio. For K/sub gate/ greater than K/sub si/, we observe a substantial coupling between source and drain regions through the gate insulator. This fact is validated by extensive device simulations with different channel length and overlap length over a wide range of dielectric permittivities. We also observe that the overlap length is an important parameter for optimizing DC performance in short channel MOS transistors. The effect of stacked gate dielectric and lateral channel engineering on the performance of high-k gate dielectric MOS transistors is also studied to substantiate the above observations.
URI: 10.1109/ICVD.2003.1183121
ISBN: 0-7695-1868-0
Appears in Collections:Proceedings papers

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