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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/397

Title: Inductance characterization of small interconnects using test-signal method
Authors: SHAH, JT
DESAI, MP
SANYAL, S
Keywords: electronics packaging
integrated circuit layout
computer simulation
interconnection networks
Issue Date: 2000
Publisher: IEEE
Citation: Proceedings of the Thirteenth International Conference on VLSI Design, Calcutta, India, 3-7 January 2000, 376-379
Abstract: The test signal method can be used to measure and model inductance parameters (self and mutual) of a very small interconnect especially in high-density ICs by using a test signal (of small known amplitude and frequency) and a DC signal along with a differential circuit. Other measurement techniques such as LCZ and TDR for measuring inductance parameters are faced with limitations of L values greater than 5nH. The test signal injection compliments this method and facilitates measurement of very low L values, especially those encountered in high speed circuits. This technique is applicable in the designing and benchmarking stage and hence is used to model interconnect couplings before packaging and polysilicon layout. An account of interconnect-substrate effects causing displacement currents that result in self-inductive effects is given. Small interconnects have been modeled as lumped elements of a transmission line to form a full system integrity analysis of the test signal injection method circuitry for circuit simulation using SPICE. A careful simulation procedure was carried out to determine the input parameters of test signal amplitude and frequency to accommodate the parasitics of the interconnect under characterization.
URI: 10.1109/ICVD.2000.812636
http://hdl.handle.net/10054/397
http://dspace.library.iitb.ac.in/xmlui/handle/10054/397
ISBN: 0-7695-0487-6
Appears in Collections:Proceedings papers

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