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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/396

Title: A state assignment scheme targeting performance and area
Authors: GUPTA, BNVM
NARAYANAN, H
DESAI, MP
Keywords: delays
finite state machines
logic partitioning
minimisation of switching nets
multivalued logic circuits
state assignment
Issue Date: 1999
Publisher: IEEE
Citation: Proceedings of the 12th International Conference On VLSI Design, Goa, India, 7-10 January 1999, 378-383
Abstract: In this paper we address the state assignment problem for Finite State Machines (FSMs). In particular we study the effect of certain sparse state encoding strategies on the area and performance of the FSM when implemented using multi-level logic circuits. We present the results of a systematic study conducted for characterizing the effects of some encoding schemes on the area and delay of FSM implementations. Based on these results, we conclude that two-hot encodings preserve the speed advantages of one-hot encodings while reducing the area of the implemented circuit. We show that the problem of finding an optimal two-hot encoding can be posed as a constrained partitioning problem on a certain graph. We describe a greedy heuristic algorithm for this partitioning problem. Finally, we present some results and comparisons between the circuits obtained using two-hot encodings as opposed to those obtained using one-hot encoding, and to those obtained using JEDI and NOVA. The results are encouraging, particularly for FSMs with a large number of states.
URI: 10.1109/ICVD.1999.745185
http://hdl.handle.net/10054/396
http://dspace.library.iitb.ac.in/xmlui/handle/10054/396
ISBN: 0-7695-0013-7
Appears in Collections:Proceedings papers

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