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Title: Interconnect delay minimization using a novel pre-mid-post buffer strategy
Authors: PRASAD, V
Keywords: Buffer Circuit
Circuit Optimisation
Integrated Circuit Design
Integrated Circuit Modelling
Issue Date: 2003
Publisher: IEEE
Citation: Proceedings of the 16th International Conference on VLSI Design, New Delhi, India, 4-8 January 2003, 417-422
Abstract: We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit. The problem can be restated as a combined buffer insertion, buffer sizing and wire sizing problem. We propose a simple buffering architecture for this problem and show that this architecture achieves a near optimal solution. We also derive simple models for a buffered wire which are suitable for high level design.
URI: 10.1109/ICVD.2003.1183171
ISBN: 0-7695-1868-0
Appears in Collections:Proceedings papers

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