Please use this identifier to cite or link to this item:
|Title:||Interconnect delay minimization using a novel pre-mid-post buffer strategy|
Integrated Circuit Design
Integrated Circuit Modelling
|Citation:||Proceedings of the 16th International Conference on VLSI Design, New Delhi, India, 4-8 January 2003, 417-422|
|Abstract:||We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit. The problem can be restated as a combined buffer insertion, buffer sizing and wire sizing problem. We propose a simple buffering architecture for this problem and show that this architecture achieves a near optimal solution. We also derive simple models for a buffered wire which are suitable for high level design.|
|Appears in Collections:||Proceedings papers|
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.