DSpace
 

DSpace at IIT Bombay >
IITB Publications >
Proceedings papers >

Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/390

Title: Fast loop matrix generation for hybrid analysis and a comparison of the sparsity of the loop impedance and MNA impedance submatrices
Authors: OVALEKAR, VRINDA S
NARAYANAN, H
Keywords: circuit analysis computing
graph theory
iterative methods
matrix algebra
Issue Date: 1992
Publisher: IEEE
Citation: Proceedings of the IEEE International Symposium on Circuits and Systems (V 4), San Diego, USA, 3-6 May 1992, 1780-1783.
Abstract: The authors report on a new method developed for loop matrix generation which is essentially an extension of the mesh matrix generation method, to handle nonplanar graphs. This method, based on J. Tarjan and R. Hopcroft's (1974) planarity testing algorithm, was found to yield sparse loop impedance matrices. For graphs with nonplanarity of 10%, the density of the resulting loop impedance matrix was less than 1%. For most networks with nonplanarities of about 2%, the number of nonzero entries was found to be less than that for the modified nodal analysis (MNA) matrix. In these cases loop analysis is expected to perform better than MNA for iterative methods of linear equation solution, both the number of iterations and the time taken for each iteration of the linear equation solution being less than that for MNA,
URI: 10.1109/ISCAS.1992.230409
http://hdl.handle.net/10054/390
http://dspace.library.iitb.ac.in/xmlui/handle/10054/390
ISBN: 0-7803-0593-0
Appears in Collections:Proceedings papers

Files in This Item:

File Description SizeFormat
230409.pdf386.55 kBAdobe PDFView/Open
View Statistics

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

 

Valid XHTML 1.0! DSpace Software Copyright © 2002-2010  Duraspace - Feedback