DSpace
 

DSpace at IIT Bombay >
IITB Publications >
Proceedings papers >

Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/387

Title: Orthogonal partitioning and gated clock architecture for low power realization of FSMs
Authors: SHELAR, RUPESH S
NARAYANAN, H
DESAI, MP
Keywords: circuit cad
finite state machines
flip-flops
integrated circuit design
integrated logic circuits
logic cad
logic partitioning
low-power electronics
Issue Date: 2000
Publisher: IEEE
Citation: Proceedings of the 13th Annual IEEE International ASIC/SOC Conference, Arlington, USA, 13-16 September 2000, 266-270.
Abstract: In this paper we address the issue of low power realization of FSMs using decomposition and gated clock architecture. We decompose the N state machine into two interacting machines with N1, N2 states such that N=N1×N2. Our cost function is the number of self-edges, which is to be maximized. For all the self-edge conditions, the inputs and clock of the respective machine is disabled to reduce the switching activity and therefore, the reduction in power can be achieved. We describe the greedy algorithm which maximizes the cost function. We attempt to keep the area the same by keeping to a minimum the number of flip-flops. We compared the results of our algorithm with JEDI. In one case, we could achieve a power reduction up to 67% with less area as well. Based on the results, we conclude that our approach is suitable for machines with a large number of states and less number of outputs.
URI: 10.1109/ASIC.2000.880713
http://hdl.handle.net/10054/387
http://dspace.library.iitb.ac.in/xmlui/handle/10054/387
ISBN: 0-7803-6598-4
Appears in Collections:Proceedings papers

Files in This Item:

File Description SizeFormat
880713.pdf492.92 kBAdobe PDFView/Open
View Statistics

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

 

Valid XHTML 1.0! DSpace Software Copyright © 2002-2010  Duraspace - Feedback