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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/343

Title: Analog circuit performance issues with aggressively scaled gate oxide CMOS technologies
Authors: NARASIMHULU, K
RAMGOPAL RAO, V
Keywords: amplifiers (electronic)
dielectric materials
leakage currents
gates (transistor)
Issue Date: 2006
Publisher: IEEE
Citation: Proceedings of the 19th International Conference on VLSI Design, Hyderabad, India, 3-7 January 2006, 1-6
Abstract: MOS transistors with sub 100 nm channel lengths need a gate oxide thickness in the range of 1-2 nm to combat the short channel effects. However at these gate dielectric thicknesses, the gate current is no longer negligible. In this paper, we report the device analog behavior with extremely scaled oxides for integrating mixed signal circuits using the scaled digital CMOS technologies. We show the performance of common source amplifiers and current mirror circuits with these technologies. Our results also show that though thin oxides result in good voltage gains of amplifier circuits, the increased gate leakage degrades the performance of current mirror circuits. We also analyze the performance of different classes of current mirror circuits in the presence of gate leakage and provide broad guidelines for analog circuit design in the presence of gate leakage.
URI: 10.1109/VLSID.2006.84
http://hdl.handle.net/10054/343
http://dspace.library.iitb.ac.in/xmlui/handle/10054/343
ISBN: 0-7695-2502-4
Appears in Collections:Proceedings papers

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