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Please use this identifier to cite or link to this item: http://dspace.library.iitb.ac.in/jspui/handle/10054/317

Title: Controlling injected electron and hole profiles for better reliability of split gate SONOS
Authors: SRIDHAR, K
BHARATH KUMAR, P
MAHAPATRA, S
MURAKAMI, E
KAMOHARA, S
Keywords: electron traps
hole traps
hot carriers
integrated circuit reliability
integrated memory circuits
network analysis
Issue Date: 2005
Publisher: IEEE
Citation: Proceedings of the 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, 27 June-1 July 2005, 190-194.
Abstract: SONOS memory cell using a split gate structure is studied using simulations. The dependence of channel hot electron (HE) and hot hole (HH) profiles (during program and erase) on bias, doping, and program gate length (LPG) is studied. The effect of trapped charge position on the threshold voltage is also studied. LPG is found to be crucial in minimizing the mismatch of HE and HH profiles as the regions of their generation are separate. Program gate voltage during program and erase is found to be the key bias for spatially adjusting the HE and HH profiles.
URI: 10.1109/IPFA.2005.1469159
http://hdl.handle.net/10054/317
http://dspace.library.iitb.ac.in/xmlui/handle/10054/317
ISSN: 0-7803-9301-5
Appears in Collections:Proceedings papers

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