Physical mechanisms for pulsed AC stress degradation in thin gate oxide MOSFETs

Abstract

An experimental study of the dielectric degradation under different AC stress conditions has been carried out using MOSFETs with 3.9 nm thick gate oxides. Bipolar and unipolar voltage pulses were used to stress the dielectric and interface state generation monitored. Pulse parameters (pulse levels, duty cycle, stress time, rise/fall times, and frequency) were systematically varied to understand the processes responsible for degradation. The experimental results give a good insight into the physical mechanisms responsible for interface degradation in ultra-thin gate oxides. The observations can be explained invoking carrier injection into the oxide followed by trapped-hole.