Please use this identifier to cite or link to this item:
Title: Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectrics
Keywords: Cmos Integrated Circuit
Dielectric Materials
Monte Carlo Methods
Leakage Currents
Issue Date: 2001
Publisher: IEEE
Citation: Proceedings of the Fourteenth International Conference on VLSI Design, Banglore, India, 3-7 January 2001, 479-482
Abstract: In this paper we look at the quantitative picture of fringing field effects by use of high-k dielectrics on the 70 nm node CMOS technologies. By using Monte-Carlo based techniques, we extract the degradation in gate-to-channel capacitance and the internal and external fringing capacitance components for varying values of K. The results clearly show the decrease in external fringing capacitance, increase in internal fringing capacitance and a slight decrease in overall capacitance, when the conventional SiO2 is replaced by high-K dielectric. From the circuit point of view the lower total capacitance will increase the speed of the device, while the internal fringing capacitance will degrade the short-channel performance contributing to higher DIBL and drain leakage.
URI: 10.1109/ICVD.2001.902704
ISBN: 0-7695-0831-6
Appears in Collections:Proceedings papers

Files in This Item:
File Description SizeFormat 
19518.pdf265.4 kBAdobe PDFThumbnail

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.